The present invention relates generally to computing devices, and more specifically to a single chip high-speed multiplication device.
High speed multiplication of binary numbers generally involves the use of an array multiplier, which can multiply two numbers in a small number of gate delays. However, multiplication of multiple precision numbers, which are numbers larger than the word width of the multiplier, involves storage and summation of numerous partial products. These must be stored until they can be added to later generated partial products, with the whole process generally taking a much longer time than single precision multiplication. In addition, different parts of the multiple precision input values must be presented to the multiplier in order to generate the desired partial products.
Current multiple precision multiplication schemes are expensive because of the sometimes excessive amount of hardware required, and often relatively slow.
It is therefore an object of the present invention to provide a single-chip multiplication device capable of multiple precision multiplication, which is fast and does not require expensive off-chip hardware. It is an object of the present invention that such multiple precision multiplication device be capable of accomplishing double precision multiplication in only four clock cycles, which is the minimum possible.